/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * Author: Gilles Talis <gilles.talis@freescale.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __DMACHMUX_VF610_H__
#define __DMACHMUX_VF610_H__

#include <asm/imx-common/dmachmux.h>

/* DMA Channel sources */
enum {
	/* DMA request sources - DMA0(MUX0)/DMA1(MUX3) */
	VF610_DMAREQSRC_UART0_RX = 2,
	VF610_DMAREQSRC_UART0_TX = 3,
	VF610_DMAREQSRC_UART1_RX = 4,
	VF610_DMAREQSRC_UART1_TX = 5,
	VF610_DMAREQSRC_UART2_RX = 6,
	VF610_DMAREQSRC_UART2_TX = 7,
	VF610_DMAREQSRC_UART3_RX = 8,
	VF610_DMAREQSRC_UART3_TX = 9,
	VF610_DMAREQSRC_SPI0_RX = 12,
	VF610_DMAREQSRC_SPI0_TX = 13,
	VF610_DMAREQSRC_SPI1_RX = 14,
	VF610_DMAREQSRC_SPI1_TX = 15,
	VF610_DMAREQSRC_SAI0_RX = 16,
	VF610_DMAREQSRC_SAI0_TX = 17,
	VF610_DMAREQSRC_SAI1_RX = 18,
	VF610_DMAREQSRC_SAI1_TX = 19,
	VF610_DMAREQSRC_SAI2_RX = 20,
	VF610_DMAREQSRC_SAI2_TX = 21,
	VF610_DMAREQSRC_PDB 	= 22,
	VF610_DMAREQSRC_FTM0_CH0 = 24,
	VF610_DMAREQSRC_FTM0_CH1 = 25,
	VF610_DMAREQSRC_FTM0_CH2 = 26,
	VF610_DMAREQSRC_FTM0_CH3 = 27,
	VF610_DMAREQSRC_FTM0_CH4 = 28,
	VF610_DMAREQSRC_FTM0_CH5 = 29,
	VF610_DMAREQSRC_FTM0_CH6 = 30,
	VF610_DMAREQSRC_FTM0_CH7 = 31,
	VF610_DMAREQSRC_FTM1_CH0 = 32,
	VF610_DMAREQSRC_FTM1_CH1 = 33,
	VF610_DMAREQSRC_ADC0 	= 34,
	VF610_DMAREQSRC_QSPI0 	= 36,
	VF610_DMAREQSRC_PORTA 	= 38,
	VF610_DMAREQSRC_PORTB 	= 39,
	VF610_DMAREQSRC_PORTC 	= 40,
	VF610_DMAREQSRC_PORTD 	= 41,
	VF610_DMAREQSRC_PORTE 	= 42,
	VF610_DMAREQSRC_RLE_RX	= 45,
	VF610_DMAREQSRC_RLE_TX	= 46,
	VF610_DMAREQSRC_SPDIF_RX = 47,
	VF610_DMAREQSRC_SPDIF_TX = 48,
	VF610_DMAREQSRC_I2C0_RX = 50,
	VF610_DMAREQSRC_I2C0_TX = 51,
	VF610_DMAREQSRC_I2C1_RX = 52,
	VF610_DMAREQSRC_I2C1_TX = 53,
	/* DMA request sources - DMA1(MUX2)/DMA0(MUX1) */
	VF610_DMAREQSRC_UART4_RX = 2,
	VF610_DMAREQSRC_UART4_TX = 3,
	VF610_DMAREQSRC_UART5_RX = 4,
	VF610_DMAREQSRC_UART5_TX = 5,
	VF610_DMAREQSRC_SAI3_RX = 8,
	VF610_DMAREQSRC_SAI3_TX = 9,
	VF610_DMAREQSRC_SPI2_RX = 10,
	VF610_DMAREQSRC_SPI2_TX = 11,
	VF610_DMAREQSRC_SPI3_RX = 12,
	VF610_DMAREQSRC_SPI3_TX = 13,
	VF610_DMAREQSRC_FTM2_CH0 = 16,
	VF610_DMAREQSRC_FTM2_CH1 = 17,
	VF610_DMAREQSRC_FTM3_CH0 = 18,
	VF610_DMAREQSRC_FTM3_CH1 = 19,
	VF610_DMAREQSRC_FTM3_CH2 = 20,
	VF610_DMAREQSRC_FTM3_CH3 = 21,
	VF610_DMAREQSRC_FTM3_CH4 = 22,
	VF610_DMAREQSRC_FTM3_CH5 = 23,
	VF610_DMAREQSRC_FTM3_CH6 = 24,
	VF610_DMAREQSRC_FTM3_CH7 = 25,
	VF610_DMAREQSRC_ADC1 	= 26,
	VF610_DMAREQSRC_QSPI1 	= 27,
	VF610_DMAREQSRC_DAC0 	= 32,
	VF610_DMAREQSRC_DAC1 	= 33,
	VF610_DMAREQSRC_ESAI_BFIFO_TX 	= 34,
	VF610_DMAREQSRC_ESAI_BFIFO_RX 	= 35,
	VF610_DMAREQSRC_I2C2_RX = 36,
	VF610_DMAREQSRC_I2C2_TX = 37,
	VF610_DMAREQSRC_I2C3_RX = 38,
	VF610_DMAREQSRC_I2C4_TX = 39,
	VF610_DMAREQSRC_ASRC1 	= 40,
	VF610_DMAREQSRC_ASRC4 	= 41,
	VF610_DMAREQSRC_ASRC2 	= 42,
	VF610_DMAREQSRC_ASRC5 	= 43,
	VF610_DMAREQSRC_ASRC3 	= 52,
	VF610_DMAREQSRC_ASRC6 	= 53,
};


#endif	/* __IOMUX_VF610_H__ */
